1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of testing the same. More specifically, this invention relates to a nonvolatile ferroelectric random access memory (FeRAM) using a ferroelectric capacitor.
2. Description of the Related Art
In these years, attention has been paid to a ferroelectric RAM (FeRAM) using a ferroelectric capacitor as a recent type of memory device (see, e.g. Jpn. Pat. Appln. KOKAI Publication No. 10-255483). The FeRAM is a memory which consists of series connected cell units (memory cells) each having a transistor (T) having a source terminal and a drain terminal and a ferroelectric capacitor (C) inbetween the two terminals, “named series connected TC unit type ferroelectric RAM”. The FeRAM has the following advantages. The FeRAM is a nonvolatile memory. The number of data write/erase operations is 1012. The data read time/write time is substantially equal to that of a DRAM (Dynamic RAM). The FeRAM permits low-voltage operations in a range of 2.5 V to 5 V. By virtue of these features, it is expected that the FeRAM will become the dominant device in all the markets of memories.
FIG. 11 shows an example of the structure of a conventional FeRAM. In this example, the FeRAM uses a shared sense amplifier scheme wherein two cell arrays are connected on both sides of a sense amplifier. As is shown in FIG. 11, each of cell arrays CA-0 and CA-1 comprises a plurality of memory blocks MB. Each memory block MB comprises a plurality of series connected memory cells (cell units) MC, each having a transistor (T) 101 and a ferroelectric capacitor (C) 102 connected in parallel. One terminal of each of the memory blocks MB is connected to a plate line PL (PL0 or PL1 in this example), and the other terminal of each memory block MB is connected to a bit line BL or /BL via an associated one of block select transistors 103. The gate of each block select transistor 103 is connected to a block select signal line BS (one of BS00, BS01, BS10 or BS11 in this example).
The gate of each cell transistor 101 is connected to a word line WL (one of WL00, WL01, . . . ,WL0n, or one of WL10, WL11, . . . ,WL1n in this example). The bit lines BL and /BL are connected to the shared-scheme sense amplifier (S/A) 105 via associated cell array select transistors 104. The gate of each cell array select transistor 104 is connected to a cell array select signal line ST (ST0 or ST1 in this example). The cell array select signal line ST0, ST1, is connected to a cell array select circuit 107.
An (n+1) number of address signal lines ADx (x=0 . . . ,n) are connected to the cell array select circuit 107. In accordance with an address signal supplied via, e.g. the address signal line ADx, the cell array select circuit 107 selects the corresponding one of the cell array select signal lines ST0 and ST1.
Of the bit lines BL and /BL, the bit line BL is connected to the drain of an n-channel metal oxide semiconductor (n MOS) transistor 106a. The source of the nMOS transistor 106a is connected to a signal line VBLR0, and the gate thereof is connected to a signal line BEQL. The bit line /BL is connected to the drain of an nMOS transistor 106b. The source of the nMOS transistor 106b is connected to a signal line VBLR1, and the gate thereof is connected to the signal line BEQL.
In the above structure, for example, as shown in FIG. 12, when memory cells MCa are to be accessed (in a normal access), the potential of the word line WL (WL01) connected to the selected memory cells MCa is set at the low level “L (LOW)”. At this time, the potential of the word lines WL other than the word line WL01 remains at the high level “H (HIGH)”. In addition, the potential of the corresponding block select signal lines BS (BS00, BS01) is set at the high level “H”. At this time, the potential of the block select signal lines BS other than the block select signal lines BS00 and BS01 remains at the low level “L”. Further, the cell array select circuit 107 sets the potential of the corresponding cell array select signal line ST (ST0) at the high level “H”. At this time, the potential of the cell array select signal line ST other than the cell array select signal line ST0 remains at the low level “L”. In this manner, the selected memory cells MCa are accessed.
As described above, in the normal access, in order to prevent damage to data, the potentials of the cell array select signal lines ST0 and ST1 are never set at the high level “H” at the same time. In short, in the conventional FeRAM, simultaneous access to the two cell arrays CA-0 and CA-1 connected to the sense amplifier 105 in a shared scheme is prohibited.
On the other hand, as shown in FIG. 13A, for example, in a fatigue test for detecting a memory cell that is likely to be fatigued, the potential of the word line WL of the memory cell MC to be tested is set at the low level “L”. In addition, the cell array select circuit 107 sets the corresponding cell array select signal line ST0 or ST1 (see FIG. 11) at the high level “H”. Further, the potentials of all the block select signal lines BS of the selected cell array CA-0 or CA-1 are set at the high level “H” (see FIG. 13B). Besides, the potential of the corresponding plate line PL and the potential of the bit lines BL and /BL are alternately swung (see FIG. 13C and FIG. 13D). In this manner, in the fatigue test, like in the normal access, only one of the two cell arrays CA-0 and CA-1, which are connected to the sense amplifier 105 in the shared scheme, is operated.
FIG. 14 shows another example of the structure of the conventional FeRAM. In this example, the FeRAM uses a shared sense amplifier scheme wherein two cell arrays are connected on both sides of a sense amplifier. As is shown in FIG. 14, each of cell arrays CA-a and CA-b comprises a plurality of memory cells (cell units) MC, each having a transistor (T) 201 and a ferroelectric capacitor (C) 202 connected in series. In the memory cells MC, one terminal of each ferroelectric capacitor 202 is connected to a plate line PL (one of PL0, PL1, PL2 and PL3 in this example), and the other terminal of each ferroelectric capacitor 202 is connected to a bit line BL or /BL via an associated one of cell transistors 201.
The gate of each cell transistor 201 is connected to a word line (one of WL00, WL01, WL02, or one of WL10, WL11, WL12 in this example). The bit lines BL and /BL are connected to the shared-scheme sense amplifier (S/A) 205 via associated cell array select transistors 204. The gate of each cell array select transistor 204 is connected to a cell array select signal line ST (ST0 or ST1 in this example). The cell array select signal line ST0, ST1, is connected to a cell array select circuit 207.
An (n+1) number of address signal lines ADx (x=0, . . . ,n) are connected to the cell array select circuit 207. In accordance with an address signal supplied via, e.g. the address signal line ADx, the cell array select circuit 207 selects the corresponding one of the cell array select signal lines ST0 and ST1.
Of the bit lines BL and /BL, the bit line BL is connected to the drain of an nMOS transistor 206a. The source of the nMOS transistor 206a is connected to a signal line VBLR0, and the gate thereof is connected to a signal line BEQL. The bit line /BL is connected to the drain of an nMOS transistor 206b. The source of the nMOS transistor 206b is connected to a signal line VBLR1, and the gate thereof is connected to the signal line BEQL.
In the above structure, for example, as shown in FIG. 15, when memory cells MCb are to be accessed (in the normal access), the potential of the word line WL (WL01) connected to the selected memory cells MCb is set at the high level “H”. The potential of the word line WL connected to the non-selected memory cells is set at the low level “L”. Further, the cell array select circuit 207 sets the potential of the corresponding cell array select signal line ST (ST0) at the high level “H”. Thereby, the selected memory cells MCb are accessed.
As described above, in the normal access time, in order to prevent damage to data, the potentials of the cell array select signal lines ST0 and ST1 are never set at the high level “H” at the same time. In short, in the conventional FeRAM having this structure, too, simultaneous access to the two cell arrays CA-a and CA-b connected to the sense amplifier 205 in the sharing scheme is prohibited.
On the other hand, as shown in FIG. 16A, for example, in a fatigue test, the potential of the word line WL of the memory cell MC to be tested is set at the high level “H”. In addition, the cell array select circuit 207 sets the corresponding cell array select signal line ST0 or ST1 (see FIG. 14) at the high level “H”. Further, the potential of the corresponding plate line PL and the potential of the bit lines BL and /BL are alternately swung (see FIG. 16B and FIG. 16C). In this FeRAM, in the fatigue test, like in the normal access, only one of the two cell arrays CA-a and CA-b, which are connected to the sense amplifier 205 in the shared scheme, is operated.
As has been described above, in the conventional FeRAM using the shared sense amplifier scheme, only one of the two cell arrays, which are connected to the sense amplifier in the shared scheme, is operated in the fatigue test, too. Consequently, the two cell arrays need to be tested individually, and this leads to an increase in test time.